How to split the gate to store energy

How does charge trapping affect a split-gate spacer memory?

Influence of charge trapping layer on programming window Split-gate spacer memories are programmed by using source side injection mode (SSI) , biasing both the memory gate and the drain electrode at high voltages, whereas the select gate potential is set in order to operate close to the threshold regime.

What is a split-gate charge trapped memory?

Split-gate charge trapped memories were fabricated with a “memory last” configuration, in which the select gate (SG) is processed first (deposited and patterned), and the memory gate (MG) is then deposited.

Does split-gate octfet reduce gate-drain capacitance-charge storage?

The split-gate OCTFET was found to have reduced gate–drain capacitance-charge storage, as represented in the HF-FOMs combining specific on-resistance with gate–drain capacitance and charge storage (RonCgd and RonQgd, respectively, Table 1 and Figure 2).

Can a split-gate flash memory be used as a charge trapping layer?

Split-gate flash memories can meet all these requirements. Different approaches can be found in the literature, using either silicon nitride (Si 3 N 4) or silicon nanocrystal (Si-nc) , as charge trapping layer.

How long is a memory gate?

Memory gates were fabricated with lengths down to 16 nm. Fig. 2. SEM plane view of select gate and memory gate (left), and schematic cross section of a split-gate memory in which the memory gate is processed as a spacer (right).

What are the requirements for a spacer memory gate?

Spacer gate has to fulfil two tricky requirements: being as flat as possible in order to get a silicidation surface as large as possible and insure a functional contact (see area 1, Fig. 3) and getting a steep edge (see area 2, Fig. 3) in order to control the drain junction doping. Fig. 3. Enlargement of the spacer memory gate. 2.2.